# Talk:Clocked logic

## intro

[edit]It seems like a worthy subject. But you need to be more intro-like in your intro. I happen to know what you are talking about, but most people would not have a clue after reading the intro :). Thue 20:46, 21 May 2004 (UTC)

- Hopefully the intro is now easier for beginners to understand. It's a technically involved subject, which makes the intro probably the hardest part to write and I wouldn't mind if someone else who knows something about the subject wants to take a stab at it. CyborgTosser 20:42, 29 Jun 2004 (UTC)

## Rename to Dynamic Logic somehow

[edit]I've been working in Silicon Valley in the field of logic and circuit design, for CPUs and later, ASICs, since 1992. I've talked with people on at least seven different full-custom CPU design teams. I've never head *anyone* refer to dynamic logic as "clocked logic". I may have seen this in the literature, however. Didn't Svennson refer to his latches as "clocked CMOS"?

I think "Clocked logic" is pretty nonstandard, and "dynamic logic" would be better. Furthermore, my guess is that there are at least thousands of circuit designers who are familiar with the term "dynamic logic" as it relates to circuits, and use it at least once a month. (Basis: there are at least 3000 people at ISSCC every year, many more that can't go for various reasons, and everyone I've talked to there knows what dynamic logic is at it applies to circuits.) I highly doubt there are anywhere near that many researchers in AI who use the phrase "dynamic logic"... there's just not enough economic activity there to pay all those people.

So I think this "clocked logic" article should be renamed "dynamic logic", and the article currently at "dynamic logic" should be renamed something else again.

Iain McClatchie 6 July 2005 03:17 (UTC)

I agree with Iains statement. It should be called dynamic logic, not clocked logic. Clocked logic to me is the "normal" single-phase kind of logic.

The "Svennson" Iain refer to is Prof Christer Svensson from University of Linköping, Sweden.

## Merge with dynamic logic

[edit]It seems like this page needs to be merged with dynamic logic - both pages say that they are synonymous, however they have completely separate articles. odd. Fresheneesz 09:00, 3 March 2006 (UTC)

- never mind... I didn't read carefully Fresheneesz 20:37, 5 March 2006 (UTC)

## What's the advantage?

[edit]Great article so far, I understand the material presented, but feel like there's something missing: why? The intro says that there are certian situations where dynamic logic has an advantage, but nothing expands on what those situations are.

Burt Harris 06:09, 8 June 2006 (UTC)

- Dynamic logic (properly designed) is over twice as fast as normal logic. It uses only fast N transistors, and is amenable to transistor sizing optimizations. Static logic is slower because it has twice the loading, higher thresholds, and actually uses slow P transistors to compute things. Domino logic may be harder to work with, but if you need the speed, there is no other choice. Anything you buy that runs over 2GHz in 2007 uses dynamic logic. Most people don't care about speed enough (or they don't have enough engineering staff and/or software) to make the extra efforts required for dynamic logic design. But Intel, AMD and IBM are notable exceptions. They really really care about speed, so they pay the staffing and software costs needed to create working dynamic logic.

Another advantage is low power. A dynamic logic circuit running at 1/2 voltage will consume 1/4 the power of normal logic. Also each rail can convey an arbitrary number of bits, and there are no power-wasting glitches. Also power-saving clock gating and asynchronous techniques are much more natural in dynamic logic.